The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to structures for a non-volatile memory and methods for forming and using such structures.
Magnetic random access memory (MRAM) provides an embedded non-volatile memory technology based on principles of magnetoresistance. Because the memory elements of the MRAM are non-volatile, the stored data is retained when the memory elements are not powered.
In an MRAM bitcell, data is stored by a magnetoresistive memory element made from a pinned magnetic layer and a free magnetic layer, each of which holds a magnetization. The magnetization of the pinned layer is fixed in its magnetic orientation, and the magnetization of the free layer can be changed by an external magnetic field generated by a programming current. In particular, the external magnetic field can cause the magnetic orientations of the magnetic layers to either be parallel, giving a lower electrical resistance across the layers (“0” state), or antiparallel, giving a higher electrical resistance across the layers (“1” state). The switching of the magnetic orientation of the free layer and the resulting high or low resistance states across the magnetic layers provide for the write and read operations of the MRAM bitcell.
A non-volatile memory includes multiple active MRAM bitcells that are arranged in an array of rows and columns. Each active bitcell in the array includes a field-effect transistor that controls access to the memory element for reading and writing data. A word line is connected to the gates of the field-effect transistors in each row of the array. The word line may be used to select the field-effect transistors in a row of active bitcells for data read and write operations to the related memory elements.
Conventional MRAM bitcells require multiple power rails in order to control read and write operations. For example, a positive gate voltage is required during write operations to switch the magnetic orientation of the free layer from parallel alignment to antiparallel alignment with the magnetic orientation of the fixed layer, and a different positive gate voltage is required during write operations to switch the magnetic orientation of the free layer from antiparallel alignment to parallel alignment with the magnetic orientation of the fixed layer. In addition, a positive voltage is supplied to either the bit line or the source line depending on the specific write operation. One approach for providing the needed power rails is to provide multiple regulated supply rails. However, this approach results in power efficiency loss in voltage regulators and increased design complexity. Another approach for providing the needed power rails is to provide internally-generated supply rails. However, this approach incurs a large area penalty. In addition to these deficiencies, the gates of the field-effect transistors must be overdriven during write operations, which may cause reliability issues.
Improved structures for a non-volatile memory and methods for forming and using such structures are needed.